The storage and video contoller of the MZ-700

The custom LSI M60719

( memory and CRT controller )

The storage / video controller of the MZ-700

Both the memory controller and the CRT controller are contained in a single chip custom LSI ( M60719 ), it has the following functions:

8 x 8 dot characters are displayed on the CRT screen of 40 characters ( horizontal ) x 25 lines ( vertical ). Displayed character font is dependent on the 4 KB character generator ( ROM ).
Manages the monitor ROM, DRAM, video RAM, and peripherals ( keyboard, timer, etc. ), mapped to the memory.
Generates clock to the Z80A microprocessor.
Selects the printer I/O port.

Storage / video controller, PAL coder ( CRT C )
can be set to NTSC by removing JP1
( see pictures to the right and above )
Customer LSI chip SHARP M60719
Circuit diagram and motherboard mark: 7A
MZ-700 SHARP Service Manual info:

NO.	PARTS CODE	PRICE RANK	NEW MARK	PART RANK	DESCRIPTION
22	VHiMZ60719GSO	BF		B	IC

Data sheet download ( PDF ) and detailed description for the M60719 will follow next. The controller signal description follows now:

Pin No.	Signal name	IN / OUT	Function	Circuit diagram signal name
1 - 16	A0 - A15	IN	CPU address bus	A0 - A15
17	LPH1	IN	Clock ( 17.7344 MHZ )	Φ ( phi )
18	PH1	IN	CPU clock ( 3.55 MHz, PHIO inverted, inverted by IC 7G )	ø ( phi )
19	CSEN	OUT	8255, 8253, joystick enable	CSE
20	CL	IN	GND	CL
21	GATE	IN	GND	GATE
22	CSON	OUT	Monitor ROM enable	CSO
23	VCC	-	Power supply	5V
24	RASN	OUT	D-RAM row address select	RAS
25	RFSN	IN	CPU refresh	RFSH
26	PHIO	OUT	CPU clock create signal ( 3.55 MHz )	øo ( phi + o )
27	MRQN	IN	CPU memory request	MREQ
28	IORN	IN	CPU I/O request	IORQ
29	RDN	IN	CPU read	RD
30	WRN	IN	CPU write	WR
31	RSTN	IN	Reset	RESET
32	SEL	IN	DRAM row / column address switching signal	SEL
33	VBLN	OUT	Vertical blanking signal ( CRT, 50 Hz )	VBLK
34	HBLN	OUT	Horizontal blanking signal ( CRT, 15.625 kHz )	HBLK
35	WATN	OUT	CPU wait	WA
36	COLR	OUT	Colour sub-carrier wave ( 4.4361875 MHz: PAL )	COLR
37	PRCN	OUT	Printer I/O address select	PRC
38 - 40	Q1 - Q3	OUT	Display: Address data output ( Line Count Signals ) ( Display address is indicated to the CG ROM together with P0 - P10 )	Q1 - Q3
41	NTPL	IN	NTSC / PAL system switching ( PAL = L )	N/P
42	BLNK	OUT	Timer clock ( 15.625 kHz )	BLNK
43	HSYN	OUT	Horizontal synchronizing signal ( 15.625 kHz )	HSY
44	ABC	OUT	unused	ABC
45	LOAD	OUT	Character, display start signal ( 1.1084 MHz = LPH1 / 16 )	LOAD
46 - 52	P0 - P6	OUT	Display address signal	P0 - P6
53	GND	-	GND
54 - 57	P7 - P10	OUT	Display address signal	P7 - P10
58	S157	OUT	V-RAM display / CPU address switching signal	S157
59	SYNN	OUT	Vertical synchronizing signal ( 50 Hz )	SYN
60	CLKN	OUT	Character display shift register clock ( 8.8672 MHz = LPH1 / 2 )	CLK

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